The inventions described and illustrated herein relate to an integrated circuit device having a memory cell array including row redundancy, and techniques for programming, configuring, controlling and/or operating such device; and more particularly, in one aspect, to an integrated circuit having random access memory (“RAM”) array having a plurality of memory cells (for example, memory cells having an electrically floating body in which an electrical charge is stored) arranged in a matrix of rows and columns wherein the integrated circuit includes a row redundancy architecture including at least one redundant row to substitute or replace a row of memory cells having at least one defective memory cell.
Briefly, with reference to FIG. 1A, memory cell array 10 typically includes a plurality of memory cells 12 arranged in a matrix of rows 14 (each typically having a common word line 16) and columns 18. A row address decoder 20 enables one or more rows to be read by sensing circuitry 22 (for example, a plurality of sense amplifiers). In order to improve, enhance and/or maintain a predetermined manufacturing yield of a memory cell array 10 and/or device, redundant rows 14r are often incorporated into memory array 10 to logically “replace” one or more rows 14 having one or more defective memory cells 12.
With reference to FIG. 1B, in one conventional technique, row redundancy is implemented by including a redundant address decoder 20r which is programmed or mapped to logically replace a defective row (i.e., a row of memory cells having one or more defective memory cells) with spare, replacement, redundant or another row 14r of memory cells 12r in memory array 10 (i.e., redundant row 14r of memory cells 12r). The individual address comparators (not illustrated) of redundant row decoder 20r are programmed to “enable” spare or redundant word line drivers 24r when the “applied” address matches the address of the defective row (which is fixed/stored in redundant row address decoder 20r). In regard, the addresses of the defective word lines 16 (which define defective row 14 of memory cells 12) are programmed into address comparators of redundant row decoder 20r during wafer testing. In this way, the redundant row address comparators enable a spare or redundant word line (which define the redundant row 14r memory cells 12) to be active when a set of row address signals match the address of a defective row 14 (or word line 16) which is programmed into redundant row address decoder 20r. 
With reference to FIG. 1C, in one conventional technique, redundant row decoder 20r is programmed via configuring the state of a set of fuses 26. In this regard, spare or redundant rows are programmed by selectively “blowing” fuses 26 within redundant row decoder 20r to “match” or correspond to the address of the rows having defective memory cells. Such fuses are often programmed prior to packaging, during the wafer testing stage, or immediately after packaging, during the device testing stage. In this way, spare or redundant word line drivers 24r are enabled when the address matches the address programmed into redundant row decoder 20r. 
Notably, circuitry 28 is implemented in memory array 10 to disable row 14 having the defective memory cells when the address matches the address programmed into redundant row decoder 20r, and spare or redundant word line drivers 24r are enabled. As such, in response to a “match” between the applied or incoming row address and the address programmed in redundant row decoder 20r, normal word line drivers 24 are disabled and redundant word line drivers 24r are enabled.